Технические дисциплины - ПППСМ

DO(8) <= PARITY_IN;

 

PROCESS(CLK)                                       --Формирование принятого байта

BEGIN

IF (CLK = '1' AND CLK'EVENT) THEN

IF (RESET = '1')

THEN DO(7 DOWNTO 0) <= "00000000";

ELSE IF (S2 = '1')

THEN IF (I = 0)

THEN DO(0) <= RX_2T;

DO(7 DOWNTO 1) <= DO(7 DOWNTO 1);

ELSE IF (I = 1)

THEN DO(1) <= RX_2T;

DO(0) <= DO(0);

DO(7 DOWNTO 2) <= DO(7 DOWNTO 2);

ELSE IF (I = 2)

THEN DO(2) <= RX_2T;

DO(1 DOWNTO 0) <= DO(1 DOWNTO 0);

DO(7 DOWNTO 3) <= DO(7 DOWNTO 3);

ELSE IF (I = 3)

THEN DO(3) <= RX_2T;

DO(2 DOWNTO 0) <= DO(2 DOWNTO 0);

DO(7 DOWNTO 4) <= DO(7 DOWNTO 4);

ELSE IF (I = 4)

THEN DO(4) <= RX_2T;

DO(3 DOWNTO 0) <= DO(3 DOWNTO 0);

DO(7 DOWNTO 5) <= DO(7 DOWNTO 5);

ELSE IF (I = 5)

THEN DO(5) <= RX_2T;

DO(4 DOWNTO 0) <= DO(4 DOWNTO 0);

DO(7 DOWNTO 6) <= DO(7 DOWNTO 6);

ELSE IF (I = 6)

THEN DO(6) <= RX_2T;

DO(5 DOWNTO 0) <= DO(5 DOWNTO 0);

DO(7) <= DO(7);

ELSE IF (I = 7)

THEN DO(7) <= RX_2T;

DO(6 DOWNTO 0) <= DO(6 DOWNTO 0);

ELSE DO(7 DOWNTO 0) <= DO(7 DOWNTO 0);

END IF;

END IF;

END IF;

END IF;

END IF;

END IF;

END IF;

END IF;

END IF;

END IF;

END IF;

END PROCESS;

 

PROCESS(CLK)                                                          --Вычисление четности

BEGIN

IF (CLK = '1' AND CLK'EVENT) THEN

IF (RESET = '1')

THEN PARITY_OUT <= '0';

ELSE IF ((S4 = '1') AND (NEW_S6 = '1') AND (PAR_EN(0) = '1'))

THEN PARITY_OUT <= DO(0) XOR DO(1) XOR DO(2) XOR DO(3) XOR

DO(4) XOR DO(5) XOR        DO(6) XOR DO(7);

ELSE IF ((S4 = '1') AND (NEW_S6 = '1') AND (PAR_EN(1) = '1'))

THEN PARITY_OUT <= NOT (DO(0) XOR DO(1) XOR DO(2) XOR

DO(3) XOR DO(4) XOR DO(5) XOR DO(6) XOR DO(7));

ELSE IF((S4 = '1') AND (NEW_S6 = '1') AND (PAR_EN(2) = '1'))

THEN PARITY_OUT <= RX_T;

ELSE PARITY_OUT <= PARITY_OUT;

END IF;

END IF;

END IF;

END IF;

END IF;

END PROCESS;

 

PROCESS(CLK)                    --Сравнение принятой и вычисленной четности

BEGIN

IF (CLK = '1' AND CLK'EVENT) THEN

IF (RESET = '1')

THEN PARITY_IN <= '0';

ELSE IF ((S4 = '1') AND (NEW_S6 = '1'))

THEN PARITY_IN <= RX_T;

ELSE PARITY_IN <= PARITY_IN;

END IF;

END IF;

END IF;

END PROCESS;

 

PROCESS(PARITY_IN, PARITY_OUT)

BEGIN

IF (PARITY_IN = PARITY_OUT)

THEN PARITY_OK <= '1';

ELSE PARITY_OK <= '0';

END IF;

END PROCESS;

 

--------------------------- BUFFER

--Автомат по формированию буфера принятых байтов

PROCESS(CLK)                                                --Секция памяти автомата

BEGIN

IF (CLK = '1' AND CLK'EVENT) THEN

IF (RESET = '1')

THEN ST0 <= '1';

ST1 <= '0';

ST2 <= '0';

ST3 <= '0';

ST4 <= '0';

ELSE ST0 <= NEW_ST0;

ST1 <= NEW_ST1;

ST2 <= NEW_ST2;

ST3 <= NEW_ST3;

ST4 <= NEW_ST4;

END IF;

END IF;

END PROCESS;

--Секция описания функции возбуждения автомата

NEW_ST0 <= RESET OR (ST0 AND (NOT S5))      OR S3 OR S4;

NEW_ST1 <= (ST0 AND S5) OR (ST1 AND (NOT TIMER2_EQ_0));

NEW_ST2 <= ST1 AND TIMER2_EQ_0;

NEW_ST3 <= ST2 AND RX_T AND RX_2T;

NEW_ST4 <= ST2 AND  (NOT (RX_T AND RX_2T));

 

PACK_RDY <= '0';--ST3;

 

------------------------------ fifo

 

PROCESS(CLK)

BEGIN

IF (CLK = '1' AND CLK'EVENT) THEN

IF (RESET = '1')

THEN ADDR_WR <= "000000";

ELSE IF (S5 = '1')

THEN ADDR_WR <= ADDR_WR + 1;

ELSE ADDR_WR <= ADDR_WR;

END IF;

END IF;

END IF;

END PROCESS;

 

PROCESS(CLK)

BEGIN

IF (CLK = '1' AND CLK'EVENT) THEN

IF (RESET = '1')

THEN ADDR_RD <= "000000";

ELSE IF (POP = '1')

THEN ADDR_RD <= ADDR_RD + 1;

ELSE ADDR_RD <= ADDR_RD;

END IF;

END IF;

END IF;

END PROCESS;

 

PROCESS(ADDR_WR, ADDR_RD)

BEGIN

IF (ADDR_WR = ADDR_RD)

THEN EMPTY <= '1';

INT   <= '0';

ELSE EMPTY <= '0';

INT   <= '1';

END IF;

END PROCESS;

 

PROCESS(CLK)

BEGIN

IF (CLK = '1' AND CLK'EVENT) THEN

IF (RESET = '1')

THEN ADDR_RD_T <= "111111";

ELSE IF (POP = '1')

THEN ADDR_RD_T <= ADDR_RD;

ELSE ADDR_RD_T <= ADDR_RD_T;

END IF;

END IF;

END IF;

END PROCESS;

 

PROCESS(ADDR_WR, ADDR_RD_T)

BEGIN

IF (ADDR_WR = ADDR_RD_T)

THEN FULL <= '1';

ELSE FULL <= '0';

END IF;

END PROCESS;

 

--Описание элементов памяти буфера

RAM64X1D_inst00 : RAM64X1D

generic map (INIT => X"0000000000000001")

port map (  DPO   => DATA2TMS(0),   -- Port A 1-bit data output

SPO   => OPEN,                          -- Port B 1-bit data output

A0    => ADDR_WR(0),             -- Port A address[0] input bit

A1    => ADDR_WR(1),             -- Port A address[1] input bit

A2    => ADDR_WR(2),             -- Port A address[2] input bit

A3    => ADDR_WR(3),             -- Port A address[3] input bit

A4    => ADDR_WR(4),             -- Port A address[4] input bit

A5    => ADDR_WR(5),             -- Port A address[5] input bit

D     => DO(0),                            -- Port A 1-bit data input

DPRA0 => ADDR_RD(0),         -- Port B address[0] input bit

DPRA1 => ADDR_RD(1),         -- Port B address[1] input bit

DPRA2 => ADDR_RD(2),         -- Port B address[2] input bit

DPRA3 => ADDR_RD(3),         -- Port B address[3] input bit

DPRA4 => ADDR_RD(4),         -- Port B address[4] input bit

DPRA5 => ADDR_RD(5),         -- Port B address[5] input bit

WCLK  => CLK,                        -- Port A write clock input

WE => S5                                    -- Port A write enable input

);

 

RAM64X1D_inst01 : RAM64X1D

generic map (INIT => X"0000000000000000")

port map (  DPO   => DATA2TMS(1),   -- Port A 1-bit data output

SPO   => OPEN,                          -- Port B 1-bit data output

A0    => ADDR_WR(0),             -- Port A address[0] input bit

A1    => ADDR_WR(1),             -- Port A address[1] input bit

A2    => ADDR_WR(2),             -- Port A address[2] input bit

A3    => ADDR_WR(3),             -- Port A address[3] input bit

A4    => ADDR_WR(4),             -- Port A address[4] input bit

A5    => ADDR_WR(5),             -- Port A address[5] input bit

D     => DO(1),                            -- Port A 1-bit data input

DPRA0 => ADDR_RD(0),         -- Port B address[0] input bit

DPRA1 => ADDR_RD(1),         -- Port B address[1] input bit

DPRA2 => ADDR_RD(2),         -- Port B address[2] input bit

DPRA3 => ADDR_RD(3),         -- Port B address[3] input bit

DPRA4 => ADDR_RD(4),         -- Port B address[4] input bit

DPRA5 => ADDR_RD(5),         -- Port B address[5] input bit

WCLK  => CLK,                         -- Port A write clock input

WE    => S5                                 -- Port A write enable input

);

RAM64X1D_inst02 : RAM64X1D

generic map (INIT => X"0000000000000000")

port map (  DPO   => DATA2TMS(2),   -- Port A 1-bit data output

SPO   => OPEN,                          -- Port B 1-bit data output

A0    => ADDR_WR(0),             -- Port A address[0] input bit

A1    => ADDR_WR(1),             -- Port A address[1] input bit

A2    => ADDR_WR(2),             -- Port A address[2] input bit

A3    => ADDR_WR(3),             -- Port A address[3] input bit

A4    => ADDR_WR(4),             -- Port A address[4] input bit

A5    => ADDR_WR(5),             -- Port A address[5] input bit

D     => DO(2),                            -- Port A 1-bit data input

DPRA0 => ADDR_RD(0),         -- Port B address[0] input bit

DPRA1 => ADDR_RD(1),         -- Port B address[1] input bit

DPRA2 => ADDR_RD(2),         -- Port B address[2] input bit

DPRA3 => ADDR_RD(3),         -- Port B address[3] input bit

DPRA4 => ADDR_RD(4),         -- Port B address[4] input bit

DPRA5 => ADDR_RD(5),         -- Port B address[5] input bit

WCLK  => CLK,                        -- Port A write clock input

WE    => S5                                 -- Port A write enable input

);

RAM64X1D_inst03 : RAM64X1D

generic map (INIT => X"0000000000000000")

port map (  DPO   => DATA2TMS(3),   -- Port A 1-bit data output

SPO   => OPEN,                          -- Port B 1-bit data output

A0    => ADDR_WR(0),             -- Port A address[0] input bit

A1    => ADDR_WR(1),             -- Port A address[1] input bit

A2    => ADDR_WR(2),             -- Port A address[2] input bit

A3    => ADDR_WR(3),             -- Port A address[3] input bit

A4    => ADDR_WR(4),             -- Port A address[4] input bit

A5    => ADDR_WR(5),             -- Port A address[5] input bit

D     => DO(3),                            -- Port A 1-bit data input

DPRA0 => ADDR_RD(0),         -- Port B address[0] input bit

DPRA1 => ADDR_RD(1),         -- Port B address[1] input bit

DPRA2 => ADDR_RD(2),         -- Port B address[2] input bit

DPRA3 => ADDR_RD(3),         -- Port B address[3] input bit

DPRA4 => ADDR_RD(4),         -- Port B address[4] input bit

DPRA5 => ADDR_RD(5),         -- Port B address[5] input bit

WCLK  => CLK,                        -- Port A write clock input

WE    => S5                                -- Port A write enable input

);

 

RAM64X1D_inst04 : RAM64X1D

generic map (INIT => X"0000000000000000")

port map (  DPO   => DATA2TMS(4),   -- Port A 1-bit data output

SPO   => OPEN,                          -- Port B 1-bit data output

A0    => ADDR_WR(0),             -- Port A address[0] input bit

A1    => ADDR_WR(1),             -- Port A address[1] input bit

A2    => ADDR_WR(2),             -- Port A address[2] input bit

A3    => ADDR_WR(3),             -- Port A address[3] input bit

A4    => ADDR_WR(4),             -- Port A address[4] input bit

A5    => ADDR_WR(5),             -- Port A address[5] input bit

D     => DO(4),                            -- Port A 1-bit data input

DPRA0 => ADDR_RD(0),         -- Port B address[0] input bit

DPRA1 => ADDR_RD(1),         -- Port B address[1] input bit

DPRA2 => ADDR_RD(2),         -- Port B address[2] input bit

DPRA3 => ADDR_RD(3),         -- Port B address[3] input bit

DPRA4 => ADDR_RD(4),         -- Port B address[4] input bit

DPRA5 => ADDR_RD(5),         -- Port B address[5] input bit

WCLK  => CLK,                        -- Port A write clock input

WE    => S5                                -- Port A write enable input

);

 

RAM64X1D_inst05 : RAM64X1D

generic map (INIT => X"0000000000000000")

port map (  DPO   => DATA2TMS(5),   -- Port A 1-bit data output

SPO   => OPEN,                          -- Port B 1-bit data output

A0    => ADDR_WR(0),             -- Port A address[0] input bit

A1    => ADDR_WR(1),             -- Port A address[1] input bit

A2    => ADDR_WR(2),             -- Port A address[2] input bit

A3    => ADDR_WR(3),             -- Port A address[3] input bit

A4    => ADDR_WR(4),             -- Port A address[4] input bit

A5    => ADDR_WR(5),             -- Port A address[5] input bit

D     => DO(5),                            -- Port A 1-bit data input

DPRA0 => ADDR_RD(0),         -- Port B address[0] input bit

DPRA1 => ADDR_RD(1),         -- Port B address[1] input bit

DPRA2 => ADDR_RD(2),         -- Port B address[2] input bit

DPRA3 => ADDR_RD(3),         -- Port B address[3] input bit

DPRA4 => ADDR_RD(4),         -- Port B address[4] input bit

DPRA5 => ADDR_RD(5),         -- Port B address[5] input bit

WCLK  => CLK,                        -- Port A write clock input

WE    => S5                                -- Port A write enable input

);

 

RAM64X1D_inst06 : RAM64X1D

generic map (INIT => X"0000000000000000")

port map (  DPO   => DATA2TMS(6),   -- Port A 1-bit data output

SPO   => OPEN,                          -- Port B 1-bit data output

A0    => ADDR_WR(0),             -- Port A address[0] input bit

A1    => ADDR_WR(1),             -- Port A address[1] input bit

A2    => ADDR_WR(2),             -- Port A address[2] input bit

A3    => ADDR_WR(3),             -- Port A address[3] input bit

A4    => ADDR_WR(4),             -- Port A address[4] input bit

A5    => ADDR_WR(5),             -- Port A address[5] input bit

D     => DO(6),                            -- Port A 1-bit data input

DPRA0 => ADDR_RD(0),         -- Port B address[0] input bit

DPRA1 => ADDR_RD(1),         -- Port B address[1] input bit

DPRA2 => ADDR_RD(2),         -- Port B address[2] input bit

DPRA3 => ADDR_RD(3),         -- Port B address[3] input bit

DPRA4 => ADDR_RD(4),         -- Port B address[4] input bit

DPRA5 => ADDR_RD(5),         -- Port B address[5] input bit

WCLK  => CLK,                        -- Port A write clock input

WE    => S5                                -- Port A write enable input

);

 

 

RAM64X1D_inst07 : RAM64X1D

generic map (INIT => X"0000000000000000")

port map (  DPO   => DATA2TMS(7),   -- Port A 1-bit data output

SPO   => OPEN,                          -- Port B 1-bit data output

A0    => ADDR_WR(0),              -- Port A address[0] input bit

A1    => ADDR_WR(1),              -- Port A address[1] input bit

A2    => ADDR_WR(2),              -- Port A address[2] input bit

A3    => ADDR_WR(3),              -- Port A address[3] input bit

A4    => ADDR_WR(4),              -- Port A address[4] input bit

A5    => ADDR_WR(5),              -- Port A address[5] input bit

D     => DO(7),                             -- Port A 1-bit data input

DPRA0 => ADDR_RD(0),          -- Port B address[0] input bit

DPRA1 => ADDR_RD(1),          -- Port B address[1] input bit

DPRA2 => ADDR_RD(2),          -- Port B address[2] input bit

DPRA3 => ADDR_RD(3),          -- Port B address[3] input bit

DPRA4 => ADDR_RD(4),          -- Port B address[4] input bit

DPRA5 => ADDR_RD(5),          -- Port B address[5] input bit

WCLK  => CLK,                         -- Port A write clock input

WE    => S5                                  -- Port A write enable input

);

 

RAM64X1D_inst08 : RAM64X1D

generic map (INIT => X"0000000000000000")

port map (  DPO   => DATA2TMS(8),   -- Port A 1-bit data output

SPO   => OPEN,                          -- Port B 1-bit data output

A0    => ADDR_WR(0),             -- Port A address[0] input bit

A1    => ADDR_WR(1),             -- Port A address[1] input bit

A2    => ADDR_WR(2),             -- Port A address[2] input bit

A3    => ADDR_WR(3),             -- Port A address[3] input bit

A4    => ADDR_WR(4),             -- Port A address[4] input bit

A5    => ADDR_WR(5),             -- Port A address[5] input bit

D     => DO(8),                            -- Port A 1-bit data input

DPRA0 => ADDR_RD(0),         -- Port B address[0] input bit

DPRA1 => ADDR_RD(1),         -- Port B address[1] input bit

DPRA2 => ADDR_RD(2),         -- Port B address[2] input bit

DPRA3 => ADDR_RD(3),         -- Port B address[3] input bit

DPRA4 => ADDR_RD(4),         -- Port B address[4] input bit

DPRA5 => ADDR_RD(5),         -- Port B address[5] input bit

WCLK  => CLK,                        -- Port A write clock input

WE    => S5                                -- Port A write enable input

);

end Behavioral;

 

 

Рис. Автомат по приему байтов.

I - счетчик битов в принимаемом байте;

DO[I] - принимаемый бит.

 

 

 

Рис. Автомат по приему пакетов



 

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